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Altera_Forum's avatar
Altera_Forum
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13 years ago

ckeck clock existent

Hello, I have two clock domains in my design 1. variable clock ~64Mhz (driven from external pll) 2. 100mhz stable clock. Does anybod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes it will create a metastability, that you can control by using several registers in cascade, all clocked at 100MHz. 3 stages should be enough. Just Google a bit for "clock domain crossing".