ymiler
Contributor
2 years agoChip planner
Hi I'd like to know how can I know how many resources exist in region lock that I choosen ? The property tab includes wrong values of DSP / M20K Do you have any user guide for it ?
Yes it is true from what sstrell was saying. From my experience this all like a floor planning. What I did is, I will compile first, in chip planner after compilation, you will the module being placed in chip, you can differentiate the module by colors, and from that you can estimate how large your logic lock is needed.
Hi
I'd like to understand what size of LL I should select. Is there an option in the "Chip Planner" tool to determine whether my selection (logic lock) is smaller or larger?
My design includes a lot of logic elements, I don't want to wait 10 hours to know if there is enough space in the LL area.
Again, you can use the compilation without LL regions as a guide. You could also create your LL region as unlocked/floating, allowing the Fitter to select a size and location for the region. You can then customize the resulting Fitter-created region based on this result (which you would want to do because the Fitter will only make it big enough to contain the assigned logic).
OK
Thank you.
what about my previous question:
I get information about the region lock from the chip planner, but it seems that something wrong with the data.
can you explain the info about the M20K below:
and what about another screenshot:
How can I have -3 ALM ???
same question about the percentage:
Quartus version 22.3