CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

Question

the Quartus STA reports "CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized"

sync-fifo in my design .

at this document "AN 919: Improving Quality of Results with Design Assistant" :https://www.intel.com/content/www/us/en/docs/programmable/683369/current/clock-domain-crossing-and-reset-domain.html

the example shows same design as I have , and it suggests to add another sample using clkb.

" the output of the blue register should feed another blue register to better protect against metastability."

but I do have 2 FF of sampling at the output - so bottom line I don't understand why my design fails at "Design Assistant (Signoff) Results"

the precise question why the STA does not "see" the sync2_in register ?

sstrell · Answer

Quartus may not be recognizing these registers as a synchronization chain.

What are your synch chain length settings (Compiler Settings -> Advanced Synthesis) and synchronizer identification settings (Timing Analyzer -> Metastability Analysis tab)?

orf · Answer

I think it is 3 ? / is it the right option ?  and auto ?

sstrell · Answer

Since it's set to 3 and you only have 2 registers in the destination clock domain, it's not getting recognized as a synch chain.  Add an extra register or reduce the chain length, though I'd recommend adding a register because it is much more common to have 2 registers in a row throughout your design so there would be a better chance of chains getting mis-identified.

orf · Answer

Hi ,

I understand your solution - Thanks! , but your last sentence is not clear "though I'd recommend adding a register because it is much more common to have 2 registers in a row throughout your design so there would be a better chance of chains getting mis-identified."

I DO have 2 registers in a row ... ( and yes all my design has 2 registers ) so I assume the recommendation should be reduce the "chain length settings" to 2 ?

Or.

sstrell · Answer

No, I'm saying to make all your synch chains at least 3 instead of reducing the chain length to 2 so that only chains of 3 get recognized as synch chains.  If you reduce the setting to 2, there most likely be many series of 2 registers mis-identified as synch chains.

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CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

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