Altera_Forum
Honored Contributor
16 years agoCarry or carry_sum !!!
Allo,
I have a problem with Carry or Carry_sum with my Design. I use Stratix III and I would juste use the carry for delay line (for A TDC Time to digital convert). Even if I set ON or OFF the 'Auto Carry Chains logic option' or 'ignore carry' in More Setting (Analysis & synthesis settings) menu, the compiler ignore this carry buffers. See my design bellow. Is there someone who has experience with this? Thank you, Jean