Carry or carry_sum !!!

Your intended structure seems basically to fit the Stratix III ALM structure in arithmetic mode. It's questionable however, if Quartus is able to compile the respective logic from your design example - or any similar construct. It may be simply unable to do it, because the intended function is too far from the ALM's expected purpose.

Did you try with the stratixiii_lcell_comb low-level primitive, as suggested in the "Stratix Cookbook" (advanced synthesis cookbook) and the related design examples?

Furthermore, considering the problem of irregular routing delays with larger logic cell delay chain designs. I guess, it's more promising, to use a group of SERDES blocks with phase shifted clocks to design a TDC.