Can't resolve multiple constant drivers?

No Problem. with VHDL you can write whatever VHDL you want and have it simulate fine, but if it isnt written with recommended coding styles you cant guarantee that the synthesised firmware will work.

Did you set any timing requirements when you say it doesnt throw any warnings?

For all VHDL you are going to synthesize, the recommended style for a clock process (to generate registers) is this:

reg_proc : process(clk, reset)
begin
  if reset = '1' then
    
    --asynchronous reset
    
  elsif rising_edge(clk) then
    
    --registered statements go here
    
    if enable = '1' then
      --register with enable statements go here
    end if;
      
  end if;
end process;

Using wait statements in process is allowed, but not a common form. It can be safer to use the rising_edge(clk) method above, because more people will have seen it and I know all synthesisors will work with it. Use wait statements to your hearts content in testbenches (where they can be very useful for creating bus functional models).

As you are new to VHDL, can I also recommend you stop using std_logic_arith and std_logic_signed/unsigned now. They are non-standard packages. They have become a bit of a defacto standard. The real IEEE standard is numeric_std, which I recommend using over the other 2 packages. it allows you to do signed and unsigned arithmatic in the same file (the other method does not) and with proper typing and much better named functions it makes more sense. It is also compatible with the new standardised fixed point libraries for doing really easy fixed point maths.

Another thing to remember is that internal ports on entites (ie. ones that dont connect to pins) can be any type you want - so use integers/boolean/enummerated types to make your code much more readable.

Any other questions, please ask away.