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Altera_Forum's avatar
Altera_Forum
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14 years ago

Can't place all RAM cells in design

Hi,

I´m using a Stratix III FPGA board EP3SL150F1152C2 and I try to build up a NiosII Core. My components are a clock, onchip memory, NIOS II Core and some more. Now I got a problem when i compile my design: 

Error (170040): Can't place all RAM cells in design
Info (170034): Selected device has 16 memory locations of type M144K block. The current design requires 24 memory locations of type M144K block to successfully fit.
Info (170033): Memory usage required for the design in the current device: 5% M9K block memory block locations required; 150% M144K block memory block locations required
 Info (170043): The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behaviour is allowed.

I don't undestand what I should change to handle the probelm. The settings for my onchip memeory are:

Block type: Auto

Data width:32

Total memory size:400000 bytes

and the rest is by default.

What should I change?

Thanks in advance for the help!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Your onchip memory is too big. The FPGA that you are using has 16 M144K blocks (256kb memory) and 355 M9K blocks (355kb). The onchip memory component can only use one type of memory block at a time and none of them can hold 400kb.

    Try to use less memory, of if you really need that much, divide it in two components. I don't know if Quartus will figure out by itself that it needs to use the two types, you may have to force the block type to M9K on one of the two components.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks!!! It works now. I just reduce the memory size how you told to do!