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Altera_Forum's avatar
Altera_Forum
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14 years ago

Can't place all RAM cells in design

Hi, I´m using a Stratix III FPGA board EP3SL150F1152C2 and I try to build up a NiosII Core. My components are a clock, onchip memory, NIOS II Core and some more. Now I got a problem when i comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks!!! It works now. I just reduce the memory size how you told to do!