Forum Discussion

Honored Contributor

8 years ago

Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

I am attempting to instantiate a signal tap core using the megafunction flow. Quartus generates the IP but when I instantiate it in my project and compile I get the following error.

Error(13785): VHDL Use Clause error at signal_tap.vhd(47): design library "altera_signaltap_ii_logic_analyzer_170" does not contain primary unit "sld_signaltap"

It works fine using .stp files but this approach doesn't fit into the flow that I'm attempting to use.

14 Replies

SDe_J
Occasional Contributor
7 years ago
Do I need to do that if I'm using the signaltap ip file instead of the GUI signaltap?
I still get this error if I enable signaltap in the settings.
sstrell
Super Contributor
7 years ago
Always. You still need a .stp file for control. That's why, in most cases, it doesn't make sense to use the Signal Tap IP instantiation flow because you need the .stp file anyway.
SDe_J
Occasional Contributor
7 years ago
Ah. I was hoping to use this as a workaround, since I can't get signaltap to work at all (as in my other post: https://forums.intel.com/s/question/0D50P00004DnM9wSAF/signaltap-problem-with-stratix-10-production-kit)
Thanks,
-Sam

Forum Discussion

Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

14 Replies

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