Can't get Quartus Prime Standard 16.1 to output SDF

I'm trying to get Quartus Prime Standard 16.1 to output SDF in order to do a gate-level simulation (in Modelsim). I have a detailed set of instructions, which were last updated for Quartus (II/Prime?) 15.0. I am following these, but no SDF is output. Has something changed since 15.0?

Needless to say, I have gone through all the settings and have searched the web and this forum for help. But no joy.

Here is the relevant bit of my instructions:

1. setup the project to use timequest:
   • select menu assignments> settings...

   • on the left, select the sub-category timequest timing analyzer

   • type counter.sdc as the sdc filename and click add.

   • click ok

2. synthesize the counter using quartus prime’s built-in vhdl synthesis tool:
   • double-click analysis & synthesis in the tasks pane on the left of quartus prime’s main window.

3. next, use timequest to create the sdc (timing constraints) file:
   • select menu tools>timequest timing analyzer (or click the toolbar icon – it looks like a blue clock.)

   • select menu netlist>create timing netlist...

   • in the create timing netlist dialog, select post-map as the input netlist and click ok.

4. you will now enter a clock constraint.
   • select menu constraints>create clock… to open the create clock dialog.

   • you can leave the clock name field blank.

   • enter a period of 10ns

   • click the button with three dots that is to the right of the target field.

   • in the name finder, with collection set to get_ports, and filter: *, click on list.

   • double-click on "clock" (or click once and then click on the ">").

   • you should see the clock as the only selected name. click ok.

   • click run in the create clock dialog.

5. at this point you might add more constraints, including ones for i/o timing. for simplicity, we will not be doing that.

6. now save the sdc file that you have created:
   • select menu constraints>write sdc file… and type counter.sdc (the same file name you entered earlier).

   • exit from timequest

7. in quartus prime, "compile" is used to refer to the whole process of implementing a design, including synthesis and place & route.
   • click the start compilation button.

   • when compilation has completed, click ok.