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Altera_Forum's avatar
Altera_Forum
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8 years ago

can't false path PLL input clock

I am getting a setup delay in my design, but the path includes the clock10 input transition time and all the time in the PLL. None of this should matter since everything is driven by the output cloc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

You're not supposed to have it ignore this delay. As you can see by the negative value in the COMP row, the PLL is compensating for the delay through the PLL and the clock network. What are you trying to do here?

If you really want no delay through the device, set the PLL mode to zero buffer delay (I think that's what it's called). That way the PLL compensated for delay all the way through the device.