"Can't elaborate user hierarchy auto_fab_0" on adding signal_tap

https://alteraforum.com/forum/attachment.php?attachmentid=15788&stc=1

Please see attachment of error.

output_files/dsa_top.syn.rpt:Error (13869):

VHDL Binding Indication error at altera_mf_components.vhd(4895): design entity "altsyncram" does not contain generic "stratixiv_m144k_allow_dual_clocks" specified in associated component File: /tools/intelFPGA_pro/18.0/quartus/libraries/vhdl/altera_mf/altera_mf_components.vhd Line: 4895

altera_mf_components.vhd:

stratixiv_m144k_allow_dual_clocks : string := "ON";

The screenshot is illegible.

But what signals are you trying to tap that make it work when they are not tapped? From the message, perhaps you are trying to tap an internal memory block signal that can't be tapped. When you add signals to Signal Tap, make sure you use the Node Finder and set the filter to "Signal Tap: pre-synthesis" (preferred since you can tap your direct RTL signals) or "Signal Tap: post-fit".

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The screenshot is illegible.

But what signals are you trying to tap that make it work when they are not tapped? From the message, perhaps you are trying to tap an internal memory block signal that can't be tapped. When you add signals to Signal Tap, make sure you use the Node Finder and set the filter to "Signal Tap: pre-synthesis" (preferred since you can tap your direct RTL signals) or "Signal Tap: post-fit".

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I am just trying to tap harmless signals such as clocks and resets. I think it is the memory used for SignalTap trace storage itself, that causes this altsyncsram error to occur.

Re-attaching a clearer screenshot here: https://imgur.com/a/yxmt0ie