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Altera_Forum
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8 years ago

"Can't elaborate user hierarchy auto_fab_0" on adding signal_tap

Hi, I have a design that uses some Altera RTL and some of my own RTL. I am trying to add a few signals to Signal Tap, but on Analysis and Elaboration, I get this error: "Error(13869)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

https://alteraforum.com/forum/attachment.php?attachmentid=15788&stc=1

Please see attachment of error.

output_files/dsa_top.syn.rpt:Error (13869):

VHDL Binding Indication error at altera_mf_components.vhd(4895): design entity "altsyncram" does not contain generic "stratixiv_m144k_allow_dual_clocks" specified in associated component File: /tools/intelFPGA_pro/18.0/quartus/libraries/vhdl/altera_mf/altera_mf_components.vhd Line: 4895

altera_mf_components.vhd:

stratixiv_m144k_allow_dual_clocks : string := "ON";