Can't create a VHDL file in Quartus

Question

Hi,

I have been trying to create a VHDL file for block diagram. The project compiles without problems, but when trying to create a HDL file for current file it shows an error. Hence I cannot progress further since I can't create symbol form file either.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11953&stc=1

Here is the screenshot of my file with errors.

Could someone help me please?

Thank you

Tom

altera_forum · Answer

The screenshot is too small to be readable. But do your signal names all meet VHDL requirements:

ie. must start with a letter. Can only contain alpha numeric characters and underscore (a-z, 0-9, _). VHDL is also case insensitive, so have you got any duplicate names through different cases. eg. nCS and ncs (same name in VHDL).

altera_forum · Answer

--- Quote Start ---

The screenshot is too small to be readable. But do your signal names all meet VHDL requirements:

ie. must start with a letter. Can only contain alpha numeric characters and underscore (a-z, 0-9, _). VHDL is also case insensitive, so have you got any duplicate names through different cases. eg. nCS and ncs (same name in VHDL).

--- Quote End ---

Hi,

thank you for getting back to me, and I do apologise for unclear screenshot.

The error message I get is: "Name "OF" contains VHDL keyword". I used symbol from quartus library BCD to 7 Segment (7447) and I would expect it to work and produce the VHDL file when prompted.

Thank you

Tom

altera_forum · Answer

The 74 series logic devices are very old and have named pins. They were probably never meant to be used with HDL.

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Can't create a VHDL file in Quartus

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