Can't create a VHDL file in Quartus

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The screenshot is too small to be readable. But do your signal names all meet VHDL requirements:

ie. must start with a letter. Can only contain alpha numeric characters and underscore (a-z, 0-9, _). VHDL is also case insensitive, so have you got any duplicate names through different cases. eg. nCS and ncs (same name in VHDL).

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Hi,

thank you for getting back to me, and I do apologise for unclear screenshot.

The error message I get is: "Name "OF" contains VHDL keyword". I used symbol from quartus library BCD to 7 Segment (7447) and I would expect it to work and produce the VHDL file when prompted.

Thank you

Tom