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Altera_Forum
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10 years ago

Can't create a VHDL file in Quartus

Hi, I have been trying to create a VHDL file for block diagram. The project compiles without problems, but when trying to create a HDL file for current file it shows an error. Hence I cannot pr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The screenshot is too small to be readable. But do your signal names all meet VHDL requirements:

ie. must start with a letter. Can only contain alpha numeric characters and underscore (a-z, 0-9, _). VHDL is also case insensitive, so have you got any duplicate names through different cases. eg. nCS and ncs (same name in VHDL).