Altera_Forum
Honored Contributor
7 years agocannot generate ddr3 core quartus 16.0
I am having a frustrating issue where i am unable to generate a ddr3 core throught the ip catalog.
I configure the core i want in the ip catalog and when go to generate the generation wizard hangs Info: ddr3_gen_0: Variation language : VHDL Info: ddr3_gen_0: Output directory : C:\repos\ddr3_ref_design Info: ddr3_gen_0: Generating variation file C:\repos\ddr3_ref_design\ddr3_gen_0.vhd Info: ddr3_gen_0: Generating synthesis files Info: Generating altera_mem_if_ddr3_emif "ddr3_gen_0" for QUARTUS_SYNTH Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_emif "ddr3_gen_0" Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_pll "pll0" Info: Generating clock pair generator Info: Generating altgpio Info: Info: ***************************** Info: Info: Remember to run the ddr3_gen_0_p0_pin_assignments.tcl Info: script after running Synthesis and before Fitting. Info: Info: ***************************** Info: Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_phy_core "p0" Info: "ddr3_gen_0" instantiated altera_mem_if_ddr3_afi_mux "m0" The wizard never get past this point..... I have tried this on quartus 15.0/16.0/17.1 on both lite and full versions of the software and it always hangs at this point... I dont know what to do? Any suggestions? Thanks