cannot generate ddr3 core quartus 16.0

I am targetting the Max10 speed grade 6. The only warnings i get are:

Warning: ddr3_max_111: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity

Warning: ddr3_max_111.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported

I am assuming the ODT is not the problem since it has to do with signal integrity. The second warning can be ignored according to:

https://www.altera.com/support/support-resources/knowledge-base/solutions/fb203048.html

I have let the wizard run over night and it still doesn't make it any further then described above...