Forum Discussion
4 Replies
- RichardT_altera
Super Contributor
Hi @shreyas
The Intel® Stratix® 10 GX 10M variant has two dies and uses DIB IP to enables direct communication between the two dies. Each die is configured separately thus you will need two Quartus projects.
In the Quartus device, you will find the device name ended with U1 and U2 - 2 separate dies. If you add the ALMs together, you will get the 3K ALMs.
You may checkout this link here for DIB related User Guide:
https://www.intel.com/content/www/us/en/programmable/documentation/wvy1588733503597.html
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. - shreyas
New Contributor
Okay, got it. Is there is any example project that we can use as a reference? Do we need to split the top-level module into two halves and synthesize separately for U1 and U2?
Best regards
Shreyas
- RichardT_altera
Super Contributor
Hi @shreyas
You can generate example design from the Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP and look for the design guidelines in the user guide.
https://www.intel.com/content/www/us/en/programmable/documentation/wvy1588733503597.html
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
- RichardT_altera
Super Contributor
Hi @shreyas
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.