ContributionsMost RecentMost LikesSolutionsRe: Cannot find Stratix-10 GX 10M FPGA (with ~3K ALMs) in quartus Okay, got it. Is there is any example project that we can use as a reference? Do we need to split the top-level module into two halves and synthesize separately for U1 and U2? Best regards Shreyas Cannot find Stratix-10 GX 10M FPGA (with ~3K ALMs) in quartus Hi, I cannot find a new Stratix-10 GX 10M FPGA with ~3K ALMs (Rightmost column here: https://www.intel.com/ content/dam/www/programmable/ us/en/pdfs/literature/pt/ stratix-10-product-table.pdf ) in Quartus (even with the latest version 20.3). Can anyone help me in finding it? My project needs an FPGA with ~3K ALMs. Thanks in advance regards Shreyas selecting Stratix 10 GX 10M largest FPGA in Quartus Hi, Does anyone know how to select a Stratix 10 GX 10M (- the largest FPGA) in Quartus? @https://blogs.intel.com/psg/intel-announces-intel-stratix-10-gx-10m-fpga-worlds-highest-capacity-with-10-2-million-logic-elements-targets-asic-prototyping-and-emulation-markets/ Thanks in advance regards Shreyas Re: How to resolve timing violations quickly No, that helped, thanks! How to resolve timing violations quickly Hi I am trying to clear timing violations of my design. But after breaking the critical paths, I need to wait for minimum of 8 hours to get the next synthesis/timing results. Is there any way to clear the timing violations by speeding the synthesis flow? Any inputs would be helpful. Thanks and regards Shreyas Communicating to stratix-10 MX device on PCI-E slot from windows host system Hi I recently added stratix-10 MX board to the PCIE 16x slot. But, I am unable to find information on how to communicate with the board from PCI express host system. Quartus programmer is not detecting the installed hardware. Is there any PCIE development kits / example designs / documentations that I can refer to? Any inputs is greatly appreciated. Thanks in advance regards Shreyas Re: How to initialize HBM memory? okay, thank you How to initialize HBM memory? Hi I am trying to simulate the HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation. Any inputs/help is greatly appreciated. Thanks in advance How to measure the external memory power consumption in FPGA's? I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of external memory like DDR3, HBM. In general, how do we measure/model the power consumption of the external memory access in Intel FPGA's? Re: Stuck at the Analysis and synthesis stage Hi Great! that worked. Thanks a lot for your help. Problem was with those memory block.