New Contributor
New ContributorOkay, got it. Is there is any example project that we can use as a reference? Do we need to split the top-level module into two halves and synthesize separately for U1 and U2?
Best regards
Shreyas
Super ContributorHi @shreyas
You can generate example design from the Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP and look for the design guidelines in the user guide.
https://www.intel.com/content/www/us/en/programmable/documentation/wvy1588733503597.html
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
