Cannot create an Internal Memory Initialization (.hex) File

Hi,

I repeated everything more thoroughly.

This time the .hex file was created.

Then I chose "Assignments->Settings->Files", added meminit.qip to the project, then recompiled it and programmed the Cyclone III using the new .sof

I was ready to see how my application could start from the internal memory.

I pressed the CPU_RESET button on my board but nothing changed.

I verified that the reset vector points to 0x0000_8000 i.e. the internal memory beginning (0x0000_8000)

So my application loaded as I believe during the FPGA configuring should run.

I examined the board scheme and guessed that the CPU_RESET button did not emulate anything like Power reset.

So I must do it myself somehow

Any idea?

Regards,

tduty

Thank you, Daixiwen!

Unfortunately my CPU does not start after configuration.

May be the reason is that I use the Altera Nios II Hardware Device Tutorial example for I don't know what tricks the Altera inserts to limit user's possibility in project modifying.

Obviously my new .sof is not able to work.

I believe every application section contains in the internal memory. But I don't know how to check it.

To verify everything was done correctly I created this project once more.

The result is the same.

What is wrong?

Regards,

tduty

Does it work when you upload the elf file to the FPGA through the EDS?

Are you sure your software project uses the bsp corresponding to your hardware project?

Hello, Daixiwen!

Every time I get the .elf file I implement "Run As->Nios II Hardware". The application is loaded into FPGA and runs.

Leds flash displaying the working counter, the Nios II - Eclipse CDT Build Console displays the numbers from counter outputs.

Then I stop the process and then repeat creating the application (I delete the project and BSP from the software folder)

Then I create memory initialization files, add meminit.qip to the hardware project, recompile it and configure the FPGA.

But the application does not work.

The bsp in my software project is created by the Nios II - Eclipse with the application project cimultaneously.

Regards,

tduty

This looks fine. Do you also use an external memory, or do you have only the internal one? If you have several memories, can you check in the bsp settings that at least the application's boot and text sections are in the internal memory?

If it's still not working, then I suggest to use signaltap on the CPU's instruction and data masters, and use a power up trigger to see what the CPU is doing when the FPGA goes out of configuration.

Not something silly like trying to use the /f nios without a real license?

Where it will only work with the jtag debug attached?

Hello,

Thank you for your advices.

1. I don’t know where to look for the application boot section but I found others.

From Linker Script tab:

Linker Section Name Linker Region Name Memory Device Name

.bss onchip_mem onchip_mem

.entry reset onchip_mem

.exceptions onchip_mem onchip_mem

.heap onchip_mem onchip_mem

.rodata onchip_mem onchip_mem

.rwdata onchip_mem onchip_mem

.stack onchip_mem onchip_mem

.text onchip_mem onchip_mem

From Linker Memory Regions tab:

Linker Region Name Address Range Memory Device Name

onchip_mem 0x00008020-0x0000CFFF onchip_mem

reset 0x00008000-0x0000801F onchip_mem

I guess the reset vector points to the application boot section or to the crt0.S startup code.

So everything must be loaded into the onchip memory.

2. I don’t know how to use signaltap on the CPU's instruction and data masters, and use a power up trigger.

So I must study how to do it. Unfortunately too many handbooks cannot be read simultaneously. Where to find the necessary text?

3. I use the Nios II/s.

Indeed my application works when I use “Run As-> Nios II Hardware” only for the time limited.

I suppose something from the example settings prevents me to achieve the success if I try to create my .hex file end the new .sof.

Regards.

tduty

Sorry the boot section is .entry. Everything looks fine.

I think there is a chapter about SignalTap in the Quartus manual. It takes some time to learn to use the tool, but it's not time wasted. It is a very useful and powerfull debugging tool, and you'll need it later. So take the time to learn it!

How do you check if your software is running? Could you for example turn a led on or off as the first instruction in main.c, just to check that the software doesn't crash later?

--- Quote Start ---

Hello, Daixiwen!

Every time I get the .elf file I implement "Run As->Nios II Hardware". The application is loaded into FPGA and runs.

Leds flash displaying the working counter, the Nios II - Eclipse CDT Build Console displays the numbers from counter outputs.

Then I stop the process and then repeat creating the application (I delete the project and BSP from the software folder)

Then I create memory initialization files, add meminit.qip to the hardware project, recompile it and configure the FPGA.

But the application does not work.

The bsp in my software project is created by the Nios II - Eclipse with the application project cimultaneously.

Regards,

tduty

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I recall that in certain versions of NIOS II Eclipse tools, after you created the memory initialization files, you have to open them in quartus:

Upon opening of the file, you would be prompted to enter the word size of the memory file, which defaults to 8 (bits).

While Nios processer is 32-bit, you simply change it to 32bits, then save and close the file, recompile the project.

I don't know why it's relevant to change the word size of the init file, but apparently it makes a difference in the results.