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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

can someone help on this

Hi all,

I am working on a finite state machine assignment. I have the following code below which i want key_0, key_1, key_2 and key_3 to influence the out LEDR[1..0] and LEDG[1..0]. key_0 and key_1 work very well when pressed the LEDG lights come on but i donot understand why key_2 and key_3 does not affect the LEDR lights when i run the code on the DE2-115 altera circuit board. I have tried to modify the code several times but still nothing happens. Thank you vhdl gurus for helping:

-----------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity uppgift_dorr is

port( clk : in std_logic; --clock signal

reset : in std_logic; --reset signal

key_0, key_1, key_2, key_3 : in std_logic;

LEDR : out std_logic_vector (1 downto 0); -- Output

LEDG : out std_logic_vector (1 downto 0) -- Output

);

end uppgift_dorr;

architecture Behavioral of uppgift_dorr is

--Defines the type for states in the state machine

type state_type is (closed,opened,locked,unlocked);

--Declare the signal with the corresponding state type.

signal Current_State, Next_State : state_type;

begin

-- Synchronous Process

process(clk, reset)

begin

if( reset = '1' ) then --Synchronous Reset

Current_State <= closed;

elsif (rising_edge(clk)) then --Rising edge of Clock

Current_State <= Next_State;

end if;

end process;

-- Combinational Process

Process(Current_State, key_0, key_1, key_2, key_3)

begin

LEDG <= "00"; LEDR <= "00";

case Current_State is

when closed =>

if ( key_0 = '1' ) then

Next_State <= closed;

LEDG <= "01";

else

Next_State <= opened;

LEDG <= "10";

end if;

when opened =>

if ( key_1 = '1' ) then

Next_State <= opened;

LEDG <= "10";

else

Next_State <= closed;

LEDG <= "01";

end if;

when locked =>

if ( key_2 = '1' ) then

Next_State <= locked ;

LEDR <= "10";

else

Next_State <= unlocked;

LEDR <= "01";

end if;

when unlocked =>

if (key_3 = '1' ) then

Next_State <= unlocked;

LEDR <= "01";

else

Next_State <= locked;

LEDR <= "10";

end if;

when others =>

NULL;

end case;

end process;

end Behavioral;

------------------------

:confused: thanks for helping

13 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Now all states are possible - does it work? have you run a testbench?

    --- Quote End ---

    ---------------------------------------

    Hi Tricky thanks again for your reply, i have run a testbench but still it does not work the way i want: i intend to have

    Key_0 pressed and LEDG(1) comes on (lights)

    Key_1 pressed and LEDG(0) comes on (lights)

    key_2 pressed and LEDR(1) comes on

    Key_3 pressed and LEDR(1), LEDR(0), LEDG(0) and LEDG(1) signifying it has come to some kind of error state which in this case is unlocked

    Below is the testbench i created can you still please take a look, other proposition from forum members are welcome as well. Feel free forum friends to add any comments that can be of help:

    -- Vhdl Test Bench template for design : uppgift_dorr

    --

    -- Simulation tool : ModelSim-Altera (VHDL)

    --

    LIBRARY ieee;

    USE ieee.std_logic_1164.all;

    ENTITY uppgift_dorr_vhd_tst IS

    END uppgift_dorr_vhd_tst;

    ARCHITECTURE uppgift_dorr_arch OF uppgift_dorr_vhd_tst IS

    -- constants

    -- signals

    SIGNAL clk : STD_LOGIC := '0';

    SIGNAL key_0 : STD_LOGIC;

    SIGNAL key_1 : STD_LOGIC;

    SIGNAL key_2 : STD_LOGIC;

    SIGNAL key_3 : STD_LOGIC;

    SIGNAL LEDG : STD_LOGIC_VECTOR(1 DOWNTO 0);

    SIGNAL LEDR : STD_LOGIC_VECTOR(1 DOWNTO 0);

    SIGNAL reset : STD_LOGIC := '0';

    COMPONENT uppgift_dorr

    PORT (

    clk : IN STD_LOGIC;

    key_0 : IN STD_LOGIC;

    key_1 : IN STD_LOGIC;

    key_2 : IN STD_LOGIC;

    key_3 : IN STD_LOGIC;

    LEDG : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

    LEDR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

    reset : IN STD_LOGIC

    );

    END COMPONENT;

    BEGIN

    i1 : uppgift_dorr

    PORT MAP (

    -- list connections between master ports and signals

    clk => clk,

    key_0 => key_0,

    key_1 => key_1,

    key_2 => key_2,

    key_3 => key_3,

    LEDG => LEDG,

    LEDR => LEDR,

    reset => reset

    );

    clk <= NOT clk after 20 ns; -- 50MHz

    reset <= '0', '1' after 100 ns;

    init : PROCESS

    -- variable declarations

    BEGIN

    key_0 <= '1';

    WAIT FOR 100 ns;

    key_1 <= '1';

    WAIT FOR 100 ns;

    key_2 <= '1';

    WAIT FOR 100 ns;

    key_3 <= '1';

    WAIT FOR 100 ns;

    key_0 <= '0';

    WAIT FOR 100 ns;

    key_1 <= '0';

    WAIT FOR 100 ns;

    key_2 <= '0';

    WAIT FOR 100 ns;

    key_3 <= '0';

    WAIT FOR 100 ns;

    WAIT;

    END PROCESS init;

    always : PROCESS

    -- optional sensitivity list

    -- ( )

    -- variable declarations

    BEGIN

    -- code executes for every event on sensitivity list

    WAIT;

    END PROCESS always;

    END uppgift_dorr_arch;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Not sure what you really want to hear - if you have a testbench then you should be able to debug the circuit yourself as you have access to all the waveforms in the simulation.

    I will comment that the key presses hold the state machine In the state - and not change the state - is that what you intended?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Not sure what you really want to hear - if you have a testbench then you should be able to debug the circuit yourself as you have access to all the waveforms in the simulation.

    I will comment that the key presses hold the state machine In the state - and not change the state - is that what you intended?

    --- Quote End ---

    --------------------------------------------

    Thanks Tricky for all your help, i have tried to implement your comment by the having the kery presses to hold the state machine in the same state but i produced a whole lot more latches again.

    I am struggling to see how i can get the code working properly. The funny thing about the wave form of the test bench in the previous case was that it gives only a few states of the code "00" and "10"

    I will continue to see how i can breakthrough this rock, your comments are still very much welcomed