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Now all states are possible - does it work? have you run a testbench?
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Hi Tricky thanks again for your reply, i have run a testbench but still it does not work the way i want: i intend to have
Key_0 pressed and LEDG(1) comes on (lights)
Key_1 pressed and LEDG(0) comes on (lights)
key_2 pressed and LEDR(1) comes on
Key_3 pressed and LEDR(1), LEDR(0), LEDG(0) and LEDG(1) signifying it has come to some kind of error state which in this case is unlocked
Below is the testbench i created can you still please take a look, other proposition from forum members are welcome as well. Feel free forum friends to add any comments that can be of help:
-- Vhdl Test Bench template for design : uppgift_dorr
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY uppgift_dorr_vhd_tst IS
END uppgift_dorr_vhd_tst;
ARCHITECTURE uppgift_dorr_arch OF uppgift_dorr_vhd_tst IS
-- constants
-- signals
SIGNAL clk : STD_LOGIC := '0';
SIGNAL key_0 : STD_LOGIC;
SIGNAL key_1 : STD_LOGIC;
SIGNAL key_2 : STD_LOGIC;
SIGNAL key_3 : STD_LOGIC;
SIGNAL LEDG : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL LEDR : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL reset : STD_LOGIC := '0';
COMPONENT uppgift_dorr
PORT (
clk : IN STD_LOGIC;
key_0 : IN STD_LOGIC;
key_1 : IN STD_LOGIC;
key_2 : IN STD_LOGIC;
key_3 : IN STD_LOGIC;
LEDG : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
reset : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : uppgift_dorr
PORT MAP (
-- list connections between master ports and signals
clk => clk,
key_0 => key_0,
key_1 => key_1,
key_2 => key_2,
key_3 => key_3,
LEDG => LEDG,
LEDR => LEDR,
reset => reset
);
clk <= NOT clk after 20 ns; -- 50MHz
reset <= '0', '1' after 100 ns;
init : PROCESS
-- variable declarations
BEGIN
key_0 <= '1';
WAIT FOR 100 ns;
key_1 <= '1';
WAIT FOR 100 ns;
key_2 <= '1';
WAIT FOR 100 ns;
key_3 <= '1';
WAIT FOR 100 ns;
key_0 <= '0';
WAIT FOR 100 ns;
key_1 <= '0';
WAIT FOR 100 ns;
key_2 <= '0';
WAIT FOR 100 ns;
key_3 <= '0';
WAIT FOR 100 ns;
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END uppgift_dorr_arch;
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