Occasional ContributorDevice used - cyclone V GT
In quartus tool , if I instantiate an adder IP , I can see, tool using ALMs to make those adders.
Since it's using ALMs ,max achievable frequency drops at this path .
So is it possible to use DSP as an adder like XILINX vivado tool ?
Regular ContributorHi,
As I understand it, you have some inquires related to implementing Adder using CV DSP block. For your information, the DSP block is primarily for multiplication. It supports pre-adder or multiply-add. It does not support single adder function. sorry for the inconvenience.
Best regards,
Chee Pin
Regular ContributorHi,
As I understand it, you have some inquires related to implementing Adder using CV DSP block. For your information, the DSP block is primarily for multiplication. It supports pre-adder or multiply-add. It does not support single adder function. sorry for the inconvenience.
Best regards,
Chee Pin
Regular ContributorHi,
For your information, I have had some discussion with my peer on this. If you refer to the "Variable Precision DSP Block Architecture for Cyclone V Devices" figure in CV device handbook, there seems to be no direct way to bypass the multiplier when you are using DSP hard block. This would explain why when you are implementing Adder, Quartus will use ALM for it.
One possible workaround that we can think of is to leveraging the pre-adder and then multiply the sum with "1". However, since this is not something validated or documented, I cannot guarantee if the design will work and how is the impact to fmax and latency. You would need to perform further evaluation to ensure the design is meeting your expectation. Hop you can understand this.
In addition to this, when you are implementing your RTL, you might need to use the LogicLock feature to force the code into DSP block just in case Quartus implement your logic into ALM.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
