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Altera_Forum
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8 years ago

Call to set_clock_groups fails for Stratix 10 Build

When my SDC file is read while compiling for a Stratix 10 device, the set_clock_groups command is failing. The failure occurs because at the point in time that the SDC file is read, the tool does no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Different behavior when re-arranging the files. Two of my clock inputs (reference clocks coming into the FPGA) that I assigned in my SDC file are already assigned by the time I get to reading it. One was only used as the reference for an IOPLL and the other was the reference clock for a full-duplex LVDS block with soft CDR. Minor problem. I'll have to get back to TimeQuest to see what name these clocks are given in order to fix the set_clock_groups command.

Thanks,