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DeepSubMicron's avatar
DeepSubMicron
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6 years ago
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C10GX serdes TX ext pll valid clk source?

For an HDMI output on an Cyclone 10 GX we need a serdes transmitter IP with reconfigurable clock.

So an LVDS SERDES with external PLL for reconfiguration.

The reference clock for most PLL should be an 50MHz input clock pin. As well for the HDMI SERDES PLL.

What are the requirements for the reference clock and how to fix this error:

Error(18694): The reference clock on PLL "pll_hdmi|iopll_0|altera_iopll_i|c10gx_pll|iopll_inst", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

Btw. the 50MHz clock pin should also be the reference clock for the DDR3 memory controller.

  • DeepSubMicron's avatar
    DeepSubMicron
    6 years ago

    Another attempt:

    Dedicated refclock input for SERDES PLL

    Other refclock input promoted to global clock with clock control instance.

    This global clock connected to all other PLLs.

    That seems to work (so far).

7 Replies

    • DeepSubMicron's avatar
      DeepSubMicron
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      6 years ago

      Does dedicated reference clock mean I can't multidrop that pin to other pll, like ddr3 memory controller?

      If the pin is driving the SERDES PLL directly then the jitter requirements for SERDES are met. At the same time driving another pll is impossible?

      • DeepSubMicron's avatar
        DeepSubMicron
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        6 years ago

        I tried to connect the ref clock input pin to other plls as well. Then an error suggest to promote clocks to global clock for the other plls. So I used a clock control instance with global clock output.

        The pll of the ddr3 memory controller does not like that because it expects a clock at PLL_CASCADE_IN which fitter tells me is incompatible to the global clock buffer output.

        So it really looks like I need another clock pin.