New ContributorAnother attempt:
Dedicated refclock input for SERDES PLL
Other refclock input promoted to global clock with clock control instance.
This global clock connected to all other PLLs.
That seems to work (so far).
Frequent ContributorHi Jens Kuenzer
Please refer to similar issue below:
We shall always use a dedicated reference clock pin per PLL that drives an Altera LVDS SERDES IP instance.
Thanks.
Eng Wei
New ContributorDoes dedicated reference clock mean I can't multidrop that pin to other pll, like ddr3 memory controller?
If the pin is driving the SERDES PLL directly then the jitter requirements for SERDES are met. At the same time driving another pll is impossible?
New ContributorI tried to connect the ref clock input pin to other plls as well. Then an error suggest to promote clocks to global clock for the other plls. So I used a clock control instance with global clock output.
The pll of the ddr3 memory controller does not like that because it expects a clock at PLL_CASCADE_IN which fitter tells me is incompatible to the global clock buffer output.
So it really looks like I need another clock pin.
New ContributorWell this more and more becomes a development blog.
After adding a dedicated pin for the PLL at the SERDES, next I tried to chain a 3rd pll to the ddr3 pll clock output.
I have tried that because it seems to me that ddr3 memory controller pll can not share ref clock input as well.
This causes an error message that IOPLL cascade chain of 3 or more IOPLLs was found:
- the ddr3 memory controller pll
- the 3rd pll
- the PLL at the SERDES (yes that with a dedicated refclock input)
Now, I am a little bit confused.
New ContributorAnother attempt:
Dedicated refclock input for SERDES PLL
Other refclock input promoted to global clock with clock control instance.
This global clock connected to all other PLLs.
That seems to work (so far).
