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New ContributorC10GX serdes TX ext pll valid clk source?
Another attempt:
Dedicated refclock input for SERDES PLL
Other refclock input promoted to global clock with clock control instance.
This global clock connected to all other PLLs.
That seems to work (so far).
New ContributorWell this more and more becomes a development blog.
After adding a dedicated pin for the PLL at the SERDES, next I tried to chain a 3rd pll to the ddr3 pll clock output.
I have tried that because it seems to me that ddr3 memory controller pll can not share ref clock input as well.
This causes an error message that IOPLL cascade chain of 3 or more IOPLLs was found:
- the ddr3 memory controller pll
- the 3rd pll
- the PLL at the SERDES (yes that with a dedicated refclock input)
Now, I am a little bit confused.
New ContributorAnother attempt:
Dedicated refclock input for SERDES PLL
Other refclock input promoted to global clock with clock control instance.
This global clock connected to all other PLLs.
That seems to work (so far).
- EngWei_O_Intel
Frequent Contributor
Hi Jens Kuenzer
Yes. Because SERDES IP data rate performance is sensitive to jitter, there is this restriction to have dedicated ref clock driving the PLL that feeds the SERDES IP.
Thanks.
Eng Wei
- DeepSubMicron
Thanks for your answer. It does not explain how adding another sink is affecting the jitter of a clock.
I mean in an FPGA it does not even increase the cap load of the driving transistors. But I am no PLL designer.
I still think the problem may be just constraining the pin placement to the iopll placement is not very intuitive. Since I failed doing so another clock pin is my workaround.
