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Mathis1's avatar
Mathis1
Icon for New Contributor rankNew Contributor
11 months ago
Solved

Bug with EDA simulation library compiler

A minor bug I think Quartus Prime Pro 24.3 Ran the EDA Simulation Library Compiler for Questa, arria 10 as the selected family Checked both boxes for Verilog and VHDL. Compilation instantly fails...
Hdl
Simulation
  • RichardT_altera's avatar
    RichardT_altera
    11 months ago

    This error does not occur in the Quartus 24.2.

    This is a valid bug in 24.3. This will be fixed in the next Quartus 25.1 release.

    1. As a workaround, use (command line interface) CLI instead of GUI. 

    quartus_sh --simlib_comp -family <device family> -tool <EDA tools> -tool_path <path to simulation tool executable> -language <verilog/vhdl> -directory <output directory> -log <filename> -cmd_file <output_cmd file> -suppress_messages

    2. Alternatively, you can tick the box in "Simulation Flow: Compatible mode for Quartus simulation flow" to generate both libs together.

    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
11 months ago

This seems like a bug. I will provide feedback to the tool developer.

You should be able to obtain the simulation libraries by selecting either Verilog or VHDL first and then compiling again with the other one.


If your source code is in VHDL but some Altera/Intel IP cores are Verilog components, it is recommended to select both Verilog and VHDL. This ensures that the Altera/Intel simulation libraries are compiled for supported simulation tools, making all required simulation models available.


Regards,

Richard Tan