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roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
2 years ago
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Bug: Import of QDB file partition fails in Quartus Pro versions that use DNI

Quartus Pro versions that use DNI fail when trying to import a partition from a QDB file. The error observed, which doesn't occur with non-DNI versions, is as follows: Error (20045): Can't find t...
Hdl
  • roeekalinsky's avatar
    roeekalinsky
    2 years ago

    Hi @SyafieqS .

    Testing with the newly released Quartus Pro 24.1, I can confirm that it fixes the original issue of this thread. Error (20045) no longer appears, and a stub file is no longer required.

    As for the other two incidentally related issues that came up in this thread:

    I can confirm that the erroneously produced Warning (21610) has also been fixed. With 24.1 this warning no longer appears.

    However, the erroneously produced Critical Warning (24035) has not been fixed. These still appear with 24.1. And this is apparently a separate issue that's independent of the stub file issues. With 24.1 it can be observed that these warnings are generated whether or not a stub file is used.

    As the original issue of this thread has been addressed in 24.1, let's close out this thread at this point. I will start a new thread to deal with the Critical Warning (24035) issue.

    Thanks,

    -Roee

SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi Roee,


Update :

Yes this is a bug in the DNI flow.

This only happens in VHDL when there is a component declaration for the precompiled module, but no actual (empty) definition for it. In classic mode it was enough to have the component definition, but in DNI mode we error out if there is no actual empty stub file.


As a workaround you can add an actual definition to the project, this definition may be empty.


For example I added a vhdl file with just this to the step 2 project for the attached design, and this makes it work:


library ieee;

use ieee.std_logic_1164.all;

entity example_core is

port (

clk : in std_logic;

i0 : in std_logic;

i1 : in std_logic;

o : out std_logic);

end example_core;

architecture rtl of example_core is

begin

end rtl;


I have requested patch for both version 23.3/23.4 and will let you know if there is any update on this.