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paw_93's avatar
paw_93
Icon for New Contributor rankNew Contributor
2 years ago

Both sides source-synchronous interface

Hi, I have a question regarding the way the sdc timing constraints affect the design. Imagine a situation where we have a source synchronous design. FPGA drives flip-flop on the ASIC side, then ASIC...
Compilation
Timing
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

It appears that you have posted two identical cases on the forum.

To ensure a more streamlined and efficient resolution process, we kindly request you to consolidate your inquiries into a single forum post.


We will continue the support in the other forum case (link below) and will transition this thread to community support.

https://community.intel.com/t5/Programmable-Devices/How-well-FPGA-adjust-delays-based-on-sdc/m-p/1592583#M95785


If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!


Regards,

Richard Tan