Block Design file issue

Hi,

I'm trying to use a block design file (.bdf) inside a (.vhd) file. I just want to connect the input of the block inside my block file (.bdf) to the input declared in the entity within the (.vhd) file. Somehow, I need to include the .bdf file in the .vhd file, but the way I'm doing it does not work (as shown below) :

For example :

library ieee;

use ieee.std_logic_1164.all;

library altera_mf;

use altera_mf.all;

------------------------------------------------------------------------

entity pll is

port(

clock_in : in std_logic;

clock_out : out std_logic

);

end pll;

------------------------------------------------------------------------

architecture pll_arch of pll is

begin

-- clk_in and clk_out are the PLL input and output pins respectively in the altpll

megafunction.

pll_instantiation : pll_block.bdf port map( clk_in => clock_in, clk_out => clock_out );

end pll_arch;

------------------------------------------------------------------------

Can we do that with QUARTUS 6.1g? - I've tried to find some info, but could not.

Regards and thanks for your help.