Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHello,
thank you for your reply. It's a good explanation for the added variable. So, I made a new vwf-file to test this, besides I erased the clock, because I don't net it. The new project: http://rapidshare.com/files/33104146/iobuff_test.zip.html (http://rapidshare.com/files/33104146/iobuff_test.zip.html) The VHDL Code works this way, that if oe='0' the value I set to "io" is shown on the output. But then I want the value on input to be shown on io~result. I set oe='1' and the value on "io" to "DC" (Don't Care). On the simulation you see, that the value an io~result (which should be the same linke "in") is unknown. I have no idea why this value is unknown. It should work like described in the VHDL Code. It makes no sense to give "io" another value for the time oe='1' because this value will be the same like on io~result. Best regards, Christian