Altera_Forum
Honored Contributor
11 years agoBest way to define a clock for TimeQuest analysis
I have a logic design for a CPLD where a clock goes out on a device pin, and comes back in on another device pin with a fixed delay (say, 10 ns).
How can I best describe the incoming clock to TimeQuest, without losing the relationship to the outgoing clock ? I guess a virtual clock is out of the question, because it loses exactly that relationship. So should it be defined as a generic clock (which, by default, will relate it to its source, although I'm not entirely sure what that means in practice) ? Or as a generated clock (incoming = outgoing + 10 ns delay) ? Or is it impossible to keep the relationship available to the analysis ? Any (informed) hints appreciated. John Kortink Windfall Engineering