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Altera_Forum's avatar
Altera_Forum
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14 years ago

Best way to code flop w/asynch reset?

Hi - I've lots of experience in Verilog, but am learning VHDL.

Question: Is this...

process(clk,rst_l) begin

if rst_l = '0' then

sig <= '0';

elsif rising_edge(clk) then

sig <= expression;

end if;

end process;

the best way to do the equivalent of

always @(posedge clk or negedge rst_l) begin

if (!rst_l) sig <= 0;

else begin

sig <= expression;

end

end

(i.e., flop with asynch reset)

I'm asking because in Verilog it's sort of by convention that if you do it -just that way- then all the synthesizers infer you want an asynch flop and the else expression is clocked. I want to make sure I'm doing it the most general way (i.e., least likely for a synth to mis-interpret) for VHDL.

THANKS!

/j

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I tend to divide my design in such a way that I get (if possible) small RTL-diagrams with only blocks, and only at the lowest level the logic will become visible. I even code a state machine in its own .vhd file so I can see what the data-flow is, without the state-machine logic cluttering the diagram. So I developed sub-modules for almost every task like counting up or down, multiplexing std_logic_vectors, priority encoders, etc., anything as long as it helps simpliying the RTL-diagram to an easy-to-follow collection of connected blocks.

    --- Quote End ---

    Excellent advice! A man after my own coding style.

    Other arguments for this approach are that you can create testbenches for each submodule, and perform code coverage.

    The other argument for splitting a state machine away from its data path logic (also known as FSM-D, or finite-state-machine data path) is that it is much easier to document. For example, FSMs drawn as algorithmic state machine (ASM) charts map directly to the case and if-then logic of both Verilog and VHDL.

    For examples of ASM charts and block diagrams that are analogous to the RTL diagrams, see:

    http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

    Cheers,

    Dave