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I tend to divide my design in such a way that I get (if possible) small RTL-diagrams with only blocks, and only at the lowest level the logic will become visible. I even code a state machine in its own .vhd file so I can see what the data-flow is, without the state-machine logic cluttering the diagram. So I developed sub-modules for almost every task like counting up or down, multiplexing std_logic_vectors, priority encoders, etc., anything as long as it helps simpliying the RTL-diagram to an easy-to-follow collection of connected blocks.
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Excellent advice! A man after my own coding style.
Other arguments for this approach are that you can create testbenches for each submodule, and perform code coverage.
The other argument for splitting a state machine away from its data path logic (also known as FSM-D, or finite-state-machine data path) is that it is much easier to document. For example, FSMs drawn as algorithmic state machine (ASM) charts map directly to the case and if-then logic of both Verilog and VHDL.
For examples of ASM charts and block diagrams that are analogous to the RTL diagrams, see:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf Cheers,
Dave
Honored Contributor
