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Altera_Forum's avatar
Altera_Forum
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11 years ago

Batch file that calls a vsim command

I have a batch file that calls vsim -c -do test.tcl, after it's done I want to execute some more code. The problem is that in the command line it stays in the vsim command and doesn't return to execute the next instructions in the batch file.

Like so:

vsim -c -do test.tcl <---- stuck here

if exist test1 del test1 <--- cant execute this

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I know very little about windows batch files, but using a sh shell under Linux I have to make sure that

    1. The tcl script passed to vsim will terminate

    2. The standard input to the vsim process is re-directed from /dev/null

    test.tcl must have a "quit -f" and something like the windows equivalent of: "vsim -c -do test.tcl < /dev/null"
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Here's a snippet from my Makefile.vsim that runs through a list of testbench files ... 

    
.PHONY: check
check: $(CONTROL_TEST_LIB_DONE)
	@cd $(CONTROL_TEST_DIR); 
	rm -f exitstatus; 
	for check in $(control_test_CHECKS); do 
		echo -n "TEST: $$check"; 
		$(VSIM) $(VSIM_ARGS) -c control_test.$$check -gmakecheck=1 
		-do "run -a; q" &> $$check.log; 
		if ; then 
			if ; then 
				echo -e "\rFAIL: $$check (see $$check.log)"; 
				rm exitstatus; 
				exit 1; 
			else 
				echo -e "\rPASS: $$check"; 
				rm exitstatus; 
			fi; 
		else 
			echo -e "\rFAIL: $$check. `pwd`/exitstatus file not found. Check the testbench."; 
			exit 1; 
		fi; 
	done

    The important bit for a testbench named testbench_tb would be ... 

    
vsim -c control_test.testbench_tb -gmakecheck=1 -do "run -a; q" &> testbench_tb.log;

    This loads the testbench that was compiled into the library control_test, sets the generic makecheck to 1 (which I use inside the testbench), runs the testbench to completion, and then "quits".

    As commented above, the bit you are missing is the quit command.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Actually I've experienced that when I have asserts in the code (even failure ones) vsim will not exit unless I redirect standard input from /dev/null

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Actually I've experienced that when I have asserts in the code (even failure ones) vsim will not exit unless I redirect standard input from /dev/null

    --- Quote End ---

    I haven't seen that issue. The main problem I found with VHDL code was that since the only way to 'exit' the testbench prior to the introduction of stop() to the VHDL standard, you always had to exit with assert false, and so the exitstatus from the process was always failure. My solution was to create an exitfile at the start of the testbench and write a failure code to it. The Makefile checks to see if that file exists to determine whether it was a true assertion failure, rather than the final assertion failure used to exit the testbench.

    Cheers,

    Dave