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Actually I've experienced that when I have asserts in the code (even failure ones) vsim will not exit unless I redirect standard input from /dev/null
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I haven't seen that issue. The main problem I found with VHDL code was that since the only way to 'exit' the testbench prior to the introduction of stop() to the VHDL standard, you always had to exit with assert false, and so the exitstatus from the process was always failure. My solution was to create an exitfile at the start of the testbench and write a failure code to it. The Makefile checks to see if that file exists to determine whether it was a true assertion failure, rather than the final assertion failure used to exit the testbench.
Cheers,
Dave
Honored Contributor
