Avalon MM templates in Qsys

ok i debounce now the buttons but i have the problem that control_go never get assert so my programm must be false. Any other hints why maybe how long to toogle data_to_buffer?

Assuming your debounced signal is active high you would create a one clock cycle pulse from it like this:

// assume debounced signal is called 'button'
reg button_d1;
wire button_edge;
 
always @ (posedge clk or posedge reset)
begin
  if (reset)
    button_d1 <= 0;
  else
    button_d1 <= button;
  end
end
 
assign button_edge = (button == 1) & (button_d1 == 0);  // creates a one cycle high pulse when button is asserted
 
// button_edge can be used to drive 'go' assuming the master isn't already operating

Thanks BadOmen i got the WriteMaster to work now but i have another quick question.

That's really only meant for writing into a memory mapped FIFO. Now that Avalon-ST exists I would say it's a useless feature since you can just export a FIFO ST sink to the top level and connect to it directly.

Hey BadOmen thanks for ur reply but i have now another question maybe u can help.

Simulating the design would make debug much easier since you'll be able to see what the master is doing when it doesn't respond with the control_done going high.

In the documentation the read master is called pipeline read master it is necessary to use a pipeline bridge betweeen read master and ddr ram?

A pipeline bridge is *not* necessary. The name just means that it supports pipelined read operations (i.e. it can post multiple reads before read data returns).

Hey badOmen my code doenst work at all. i got following problems.

							
wire  data ;				// 4 Byte Data
wire control_fixed_location;
wire  control_write_base;
wire  control_write_length;
wire  control_read_base;
wire  control_read_length;
wire control_go_write;
wire control_go_read;
wire data_to_buffer;                    //  write data to  fifo
wire control_done_write;
wire control_done_read;
wire read_buffer_done;                  // read value from fifo -> next value
wire read_data_available;              // data in fifo
wire 	button_pio_deb;            // debouced buttons
assign control_fixed_location = 1'b0;
assign control_write_base = 32'h08FFFFAC;
assign control_write_length = 32'h00000004;
assign control_read_base = 32'h08FFFFB8;
assign control_read_length = 32'h00000008;
reg control_go_reg =1'b0;          //write command
reg control_go_reg_read =1'b0;     //  read command
reg data_to_buffer_reg=1'b0;       //  write data to fifo
reg read_buffer_done_reg = 1'b0;   // read value from fifo -> next value
reg led_pio_reg_1=1'b1;            // ledflag
reg led_pio_reg_2=1'b1;             // ledflag
reg button_old_1=1'b1;
reg button_new_1=1'b1;
reg button_old_2=1'b1;
reg button_new_2=1'b1;
reg read_or_write=1'b0;           // toogle between read and write with buttons (read init)
reg  data_read_reg = 32'h00000000; //  Read data to Write data
reg  data_read_reg_2 = 32'h00000000; //  Read data to Write data
reg flag =1'b0;
reg flag2 =1'b0;
Debounce Debounce_1(
      .clk(clkin_100),
		.keyin(button_pio),
		.keyout(button_pio_deb)	
);
Debounce Debounce_2(
      .clk(clkin_100),
		.keyin(button_pio),
		.keyout(button_pio_deb)	
);
always @(posedge clkin_100)
begin
     button_old_1 <= button_new_1;
     button_new_1 <= button_pio_deb;
     button_old_2 <= button_new_2;
     button_new_2 <= button_pio_deb;
 
 
  if(read_or_write==1'b0) begin
   
	if ( button_new_1==1'b0 && button_old_1==1'b1)  begin
		     control_go_reg_read <= 1'b1 ; 
                          control_go_reg<= 1'b0;
		data_to_buffer_reg <= 1'b0;  
		    
			  
	 end
	 else  begin
				control_go_reg_read<= 1'b0; 
	 end
	 
	 
    if ( button_new_2==1'b0 && button_old_2==1'b1 && read_data_available==1'b1)  begin
	     if((flag==1'b0) & (flag2==1'b0)) begin
	       data_read_reg <= data;
		    read_buffer_done_reg <= 1'b1 ; 
			 flag<=1'b1;
			 led_pio_reg_1<= 1'b1;
			end
			else if ((flag==1'b1) & (flag2==1'b0)) begin	
			data_read_reg_2 <= data;
			read_buffer_done_reg <= 1'b1 ;
			  
		    
			 led_pio_reg_1<= 1'b0;
			 read_or_write<=1'b1;
			 flag2<=1'b1;
			 end
			 
	 end
	 else  begin
				read_buffer_done_reg <= 1'b0; 
	 end
   
 
 end // if read_or_write
 
	if(read_or_write==1'b1) begin
 
    if ( button_new_1==1'b0 && button_old_1==1'b1)  begin
		     control_go_reg <= 1'b1 ;   		  
			  read_or_write<=1'b0;
			  flag<=1'b0;
			  flag2<=1'b0;
			  
	 end
	 else  begin
				control_go_reg<= 1'b0; 
                                                   read_buffer_done_reg <= 1'b0;
		                           control_go_reg_read<= 1'b0;
	 end
	 
	 
    if ( button_new_2==1'b0 && button_old_2==1'b1)  begin
		     data_to_buffer_reg <= 1'b1 ;   
		  
	 end
	 else  begin
				data_to_buffer_reg <= 1'b0; 
	 end
 
	end // if read_or_write
	
	
end
assign data_to_buffer = data_to_buffer_reg;
assign control_go_write = control_go_reg;
assign control_go_read=control_go_reg_read;
assign  read_buffer_done=read_buffer_done_reg;
assign data = data_read_reg_2;
assign led_pio = control_done_read;
assign led_pio = read_data_available;
assign led_pio = read_or_write;
assign led_pio = control_done_write;

Hey i try some new code without the buttons but it still now work how long i must assert user_write_buffer ? i assert ein cycle (10ns) is that enongh?