Avalon Clock Crossing Bridge with write response support

Thanks for the hint, but that gives me only the completion of the Avalon write transaction to the Clock Crossing Bridge, but not to the final target.

But if you have a multi master scenario this cannot be used to tell, when data actually is written to the target.

E.g. the following scenario:

In this case the DMA controller cannot know when the Clock crossing bridge actually completes the transfer due to the variable delay of its internal FIFO. Thus it may happen, that the Interrupt to the NIOS arrives too early and the data is not yet written to the external memory.

It depends on the overall load on the shared EMIF Avalon MM Interface and the fillstate of the FIFO in the clock crossing bridge.

The risk that this happens may be reduced by reducing the size of the clock crossing bridge FIFO and by adding additional wait cycles before issuing the ISR, but so far I have not found a reliable way to guarantee a coherent execution order.

Any suggestions on this scenario?

best regards

Fabian