Forum Discussion
Avalon Clock Crossing Bridge with write response support
- 1 year ago
Hi Fabian,
If so, I would suggest you to use Clock crossing adapter type handshake check this link https://www.intel.com/content/www/us/en/docs/programmable/683609/24-1/interconnect-parameters-59023.html to enforce that each write must fully complete before the next is accepted
Thanks,
Regards,
Sheng
Hi Fabian,
Avalon Clock Crossing Bridge didn't use the write response and write response valid signals.
Btw, you may refer to the waitrequest (low) and write signals (low) for complete transaction. Check this link https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html
A write command is considered accepted when the last beat of the burst is issued to the agent and waitrequest is low.
Thanks,
Regards,
Sheng