Altera_Forum
Honored Contributor
14 years agoAutomating multiple VHDL simulations in ModelSim
Hello,
I'll try to explain my problem, I'm sorry if there are some English mistakes. I have my design in VHDL, and several VHDL testbenches, each of them simulates one component of my design. I'm using tcl files to automate the simulation for each testbench, one after the other. Below is a short version of my files: go.bat : start "Simulation of Design" /WAIT vsim -runinit -do "do All_Simulations.do" all_simulations.do: do Start_Simulation.do [set simulation [list {RTL arch1}]] do Start_Simulation.do [set simulation [list {RTL arch2}]] … start_simulation.do: # # Compilation ... ... # Simulation vsim -t 1ps -L lpm -L altera_mf -coverage work.testbench run -all quit -sim # Save coverage reports coverage save -code bcefs -instance sim:/testbench/top_inst ../RESULT/UCDB/${ARCH_SIM}.ucdb The first simulation goes well until the last line of my VHDL testbench, which is "report severity failure", is reached. My script is stuck at "run -all", and in ModelSim I see vsim <paused> I was wondering if there were a way to quit the simulation, and not Modelsim? Maybe include something in my VHDL code? I tried to use "stop" and "finish" from ENV package without success, indeed "stop" doesn't change anything and "finish" makes Modelsim quit. I would be really glad if you could help me !! Thank you Damien