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Altera_Forum
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13 years ago

Automating multiple VHDL simulations in ModelSim

Hello, I'll try to explain my problem, I'm sorry if there are some English mistakes. I have my design in VHDL, and several VHDL testbenches, each of them simulates one component of my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

As expected this doesn't make any difference.

I found a beginning of a solution by using the onbreak command before "run -all":

onbreak {

coverage save -code bcefs -instance sim:/testbench/top_inst ../RESULT/UCDB/${ARCH_SIM}.ucdb

quit -sim

}

run -all

My .ucdb is saved and correct but "quit -sim" seems to be invisible