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Altera_Forum
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13 years ago

Automating multiple VHDL simulations in ModelSim

Hello, I'll try to explain my problem, I'm sorry if there are some English mistakes. I have my design in VHDL, and several VHDL testbenches, each of them simulates one component of my desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Simulations will automaticcally stop at event starvation (like you stop the clock). it should also stop on a assert failure.

but to quit the sim, and not modelsim, you can type:

quit -sim