Forum Discussion

Honored Contributor

13 years ago

Automating multiple VHDL simulations in ModelSim

Hello, I'll try to explain my problem, I'm sorry if there are some English mistakes. I have my design in VHDL, and several VHDL testbenches, each of them simulates one component of my desi...

Altera_Forum

Honored Contributor

13 years ago

Did you pass stop() an argument? You need to use stop(1).

There's a VHDL testbench example modelsim_example.zip posted in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

Cheers,

Dave

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Automating multiple VHDL simulations in ModelSim

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