Forum Discussion
I'm wondering if anyone else has had success with this? I am looking at doing the same thing and it's not very intuitive when adding source files in the Component Generation GUI. The .QSYS and/or .QIP are typically the sources of truth with a list of source files + SDC, etc for a piece of IP. These are perfect to use when adding IP to Quartus project directly. But, if you add these to the fileset (via the GUI) and then select "Analyze Synthesis Files" as a sanity check, it comes back that there is a "null" file to process.
If you select the synth/[ip_name].v file, it passes the synthesis test, but I don't know how the _hw.tcl would ultimately be aware that there are sub-modules to the generated IP (FIFO) with the [ip_name]_xxxxxxx.v that are uniquely generated when building the IP in Qsys.
In this case, trying to create a _hw.tcl custom component that is instantiating a basic FIFO via IP.
Any insight into this would be fantastic! Thanks in advance.