Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi, this is not what I meant. My custom ip contains my own vhdl which i assigned into my _hw.tcl file. So when generating qsys the vhdl for my component will be generated into the synthesis directory of my qsys system. However, my component also uses two quite complex megawizard generated components such as an alt_xcvr_reconfig variant and also a altera_xcvr_custom variant.
In my _hw.tcl I only included the toplevel generated vhdl files for these megawizard generated files (the ones that contain all megawizard parameters). But... of course the real code is generated in special directories with a bunch of verilog and system_verilog files. Beside that the megawizard generated .qip files for both components which really describe which files belong to these ip. So... I can do two things : 1. manually add these qip files to my project 2. ignore it and generate the qsys. If I choose this option then during synthesis ofcourse the design files belonging to these components are not found. 3. I could paste the content of these qip files into the add_fileset_file lines to my _hw.tcl which becomes a mess of files... but it is possible Therefore I would like a manner to include the contents of the qip and see all files included in the add_fileset_add lines OR an option which automatically adds my two qip files which in fact are parts of my custom ip to the .qsf file. Adding the qsys to the quartus project does not solve my issue as described above. regards