Hi Tzi Khang,
Thank you for the help! Below are my itemized responses to your questions:
(1) My setting has been the same as you instructed in Pic 2 & 3. As for Pic 4, however, the picture seems to be largely compressed by the forum and the resolution is too low to see the content clearly. May I ask if you can post it somewhere else (e.g., on
https://imgur.com/) and post the link here again?
(2) I was not trying to convert the sof file to other programming file formats. Instead, I was just trying to re-compile the design. The reason for this recompilation was that, when I opened the arria 10 Avalon-MM DMA reference design (
http://www.alterawiki.com/wiki/reference_design:_gen3x8_avmm_dma_-_arria_10) in Quartus 17, I was told by the tool that the Qsys IP (PCIe IP) used in that reference design needs to be upgraded; since the reference design was created with Quartus 16.0, I think this upgrade makes sense. However, after upgrading the IP in Qsys, I clicked the "compile" button again, and Quartus threw the Error 210027 message at the assembler step.
(3) Please see the assembler error message below:
Assembler report for top
Mon Nov 13 10:50:13 2017
Quartus Prime Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Encrypted IP Cores Summary
5. Assembler Generated Files
6. Assembler Device Options: top.sof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable
agreement for further details.
+-----------------------------------------------------------+
; Assembler Summary ;
+-----------------------+-----------------------------------+
; Assembler Status ; Failed - Mon Nov 13 10:50:13 2017 ;
; Revision Name ; top ;
; Top-level Entity Name ; top_hw ;
; Family ; Arria 10 ;
; Device ; 10AX115S2F45I1SG ;
+-----------------------+-----------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+------------------------------------------------+
; Assembler Encrypted IP Cores Summary ;
+--------+------------------------+--------------+
; Vendor ; IP Core Name ; License Type ;
+--------+------------------------+--------------+
; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ;
; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ;
+--------+------------------------+--------------+
+---------------------------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------------------------------------------------------+
; /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/output_files/top.sof ;
+---------------------------------------------------------------------------------------------------------------------+
+-----------------------------------+
; Assembler Device Options: top.sof ;
+----------------+------------------+
; Option ; Setting ;
+----------------+------------------+
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x30A76529 ;
+----------------+------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition
Info: Processing started: Mon Nov 13 10:49:07 2017
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top
Info: Using INI file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/quartus.ini
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error (210027): Can't use configuration device EPCQL256 with selected programming mode
Error: Quartus Prime Assembler was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 8534 megabytes
Error: Processing ended: Mon Nov 13 10:50:14 2017
Error: Elapsed time: 00:01:07
Error: Total CPU time (on all processors): 00:01:22
(4) I am using the Arria 10 GX FPGA Dev Kit (
https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html) out of box. I am not sure how to identify some of the information you requested, such as memory type, JTAG/AS/etc header, etc.
(5) Do I have to install anything other than the Quartus software and the Arria 10 device file to compile the reference design?
Thank you very much for providing the help!
Honored Contributor
