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Altera_Forum
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16 years ago

Assignment pin problem. Work and do not work?

Hi every one, thank you in advance if someone could help me or tell me some ideas to get my project works. I do not know what problem is:

- My project is done on CyloneIII 3C25 Stater FPGA board.

(I reused standard example of CyloneIII 3C25 Stater kit to develop my project.

- I built a component on SOPC with interface signals to external device as following:

--- Quote Start ---

output clk;

inout cmd;

inout data1;

inout data2;

inout data3;

inout data4;

--- Quote End ---

With inout signal above, in my verilog code, i do this code segment: 


assign cmd = cmd_out_en ? cmd_out : 1'b Z;
assign data1 = data0_out_en ? data0_out : 1'b Z;
assign data2 = data1_out_en ? data1_out : 1'b Z;
assign data3 = data2_out_en ? data2_out : 1'b Z;
assign data4 = data3_out_en ? data3_out : 1'b Z;

I meet 2 problem:

First)

When i finished building SOPC component (every thing is ready for compilation on Quartus8.0), i started Analysis and Synthesis on Quartus8.0. After that, i intended to map my component pins (clk, cmd, data1, data2, data3, data4) with FPGA pin. But in Assignment pin window of Quartus, It did not generate my component pins (clk, cmd, data1, data2, data3, data4). There are some thing was wrong here, if not these my component pins must be see in Assignment pin window.

I re-install my PC and Quartus8.0 software. Then did again, this time, these component pins were see in Assignment pin Window. So i pass this problem although do not know the problem where is!

Second)

When i passed 1st problem above, i started test my project. I used Signal Tap to capture all signals have been listed above. It seem that the segment code i have show above did not work. Because :

- cmd always equal cmd_out although cmd_out_en is 0 logic level or 1 logic level

- data1, data2, data3, data4 are similar cmd.

- About clk, it is a clock signal, i could see it worked in Signal Tap, but i used a oscilloscope to monitored pin of external device that map with this clk pin of my component. it did not reflect wave form of clk pin in signal tap (Oscilloscope always show as only on logic level without changing at all times).

I was afraid that it may be external device pins did not connect with pin FPGA, so i had do a simple test and use oscilloscope monitors to compare with my 2nd problem. But this test worked.

So, i guess that although in Assignment pin Window of Quartus8.0 have pins of my component, i mapped my component pins to FPGA pin, but it is actual that due to some things, Quartus compilation could not connect my component pins with FPGA pins.

Could you help me? I thank you in advance!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Yes, thank you, Hardik.

    This is the *.tcl of my component. 

    
#  TCL File Generated by Component Editor 8.0
#  Thu Oct 08 16:53:40 ICT 2009
#  DO NOT MODIFY
#  +-----------------------------------
#  | 
#  | tea_top "tea_top" v1.0
#  | null 2009.10.08.16:53:40
#  | 
#  | 
#  | D:/TEA/Fpga_TEA/TEA_3C25_0/tea_src/tea_top.v
#  | 
#  |    ./tea_top.v syn, sim
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | module tea_top
#  | 
set_module_property NAME tea_top
set_module_property VERSION 1.0
set_module_property GROUP ""
set_module_property DISPLAY_NAME tea_top
set_module_property TOP_LEVEL_HDL_FILE tea_top.v
set_module_property TOP_LEVEL_HDL_MODULE tea_top
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property SIMULATION_MODEL_IN_VERILOG false
set_module_property SIMULATION_MODEL_IN_VHDL false
set_module_property SIMULATION_MODEL_HAS_TULIPS false
set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | files
#  | 
add_file tea_top.v {SYNTHESIS SIMULATION}
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | parameters
#  | 
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | connection point avalon_slave_0
#  | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
set_interface_property avalon_slave_0 bridgesToMaster ""
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 addressSpan 1024
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_sink
add_interface_port avalon_slave_0 rbus_slv_addr address Input 8
add_interface_port avalon_slave_0 rbus_slv_wr_data writedata Input 32
add_interface_port avalon_slave_0 rbus_slv_wr_strb write Input 1
add_interface_port avalon_slave_0 rbus_slv_rd_strb read Input 1
add_interface_port avalon_slave_0 rbus_slv_rd_data readdata Output 32
add_interface_port avalon_slave_0 rbus_slv_ack waitrequest_n Output 1
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | connection point clock_sink
#  | 
add_interface clock_sink clock end
set_interface_property clock_sink ptfSchematicName ""
add_interface_port clock_sink clk_sys clk Input 1
add_interface_port clock_sink rstsys_n reset_n Input 1
#  | 
#  +-----------------------------------
#  +-----------------------------------
#  | connection point conduit_end
#  | 
add_interface conduit_end conduit end
set_interface_property conduit_end ASSOCIATED_CLOCK clock_sink
add_interface_port conduit_end clk export Output 1
add_interface_port conduit_end cmd export Bidir 1
add_interface_port conduit_end data1 export Bidir 1
add_interface_port conduit_end data2 export Bidir 1
add_interface_port conduit_end data3 export Bidir 1
add_interface_port conduit_end data4 export Bidir 1
add_interface_port conduit_end rbus_slv_byte_en export Input 4
#  | 
#  +-----------------------------------